The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 27, 2021

Filed:

Oct. 10, 2019
Applicant:

Power Integrations, Inc., San Jose, CA (US);

Inventors:

Alexey Kudymov, Ringoes, NJ (US);

Jamal Ramdani, Lambertville, NJ (US);

Assignee:

POWER INTEGRATIONS, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/07 (2006.01); H01L 27/06 (2006.01); H01L 21/8252 (2006.01); H01L 29/06 (2006.01); H01L 29/737 (2006.01); H01L 29/205 (2006.01); H01L 29/66 (2006.01); H01L 29/86 (2006.01); H01L 29/165 (2006.01); H01L 29/778 (2006.01); H01L 29/8605 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0629 (2013.01); H01L 21/8252 (2013.01); H01L 27/0605 (2013.01); H01L 29/0642 (2013.01); H01L 29/165 (2013.01); H01L 29/205 (2013.01); H01L 29/66196 (2013.01); H01L 29/66318 (2013.01); H01L 29/737 (2013.01); H01L 29/7787 (2013.01); H01L 29/86 (2013.01); H01L 29/8605 (2013.01); H01L 29/0649 (2013.01); H01L 29/2003 (2013.01); H01L 29/7786 (2013.01);
Abstract

A heterostructure semiconductor device includes first and second active areas, each electrically isolated from one another, and each including first and second active layers with an electrical charge disposed therebetween. A power transistor is formed in the first active area, and an integrated gate resistor is formed in the second active area. A gate array laterally extends over the first active area of the power transistor. First and second ohmic contacts are respectively disposed at first and second lateral ends of the integrated gate resistor, the first and second ohmic contacts are electrically connected to the second portion of the second active layer, the second ohmic contact also being electrically connected to the gate array. A gate bus is electrically connected to the first ohmic contact.


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