The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 27, 2021
Filed:
Mar. 06, 2020
Atomera Incorporated, Los Gatos, CA (US);
Nyles Wynn Cody, Tempe, AZ (US);
Keith Doran Weeks, Chandler, AZ (US);
Robert John Stephenson, Duxford, GB;
Richard Burton, Phoenix, AZ (US);
Yi-Ann Chen, Campbell, CA (US);
Dmitri Choutov, Sunnyvale, CA (US);
Hideki Takeuchi, San Jose, CA (US);
Yung-Hsuan Yang, San Jose, CA (US);
ATOMERA INCORPORATED, Los Gatos, CA (US);
Abstract
A method for making a semiconductor device may include forming an isolation region adjacent an active region in a semiconductor substrate, and selectively etching the active region so that an upper surface of the active region is below an adjacent surface of the isolation region and defining a stepped edge therewith. The method may further include forming a superlattice overlying the active region. The superlattice may include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.