The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 27, 2021

Filed:

Aug. 26, 2019
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Peter Rabkin, Cupertino, CA (US);

Kwang-Ho Kim, Pleasanton, CA (US);

Masaaki Higashitani, Cupertino, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 11/34 (2006.01); G11C 16/06 (2006.01); G11C 16/14 (2006.01); G11C 16/30 (2006.01); H03H 11/28 (2006.01); G11C 16/34 (2006.01); H01L 27/11582 (2017.01); H01L 27/11556 (2017.01);
U.S. Cl.
CPC ...
G11C 16/06 (2013.01); G11C 16/0483 (2013.01); G11C 16/14 (2013.01); G11C 16/30 (2013.01); G11C 16/3445 (2013.01); H03H 11/28 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01);
Abstract

A memory system is provided with technology for performing temperature dependent impedance mitigation, in addition to or instead of other techniques to compensate for differences in impedance. For example, the memory system comprises a plurality of non-volatile memory cells, a first pathway connected to the plurality of non-volatile memory cells, a second pathway connected to the plurality of non-volatile memory cells, and a control circuit connected to the first pathway and the second pathway. The control circuit is configured to compensate based on temperature for a temperature dependent impedance mismatch between the first pathway and the second pathway during a memory operation on the plurality of non-volatile memory cells.


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