logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11074391 B1

PDFFull Text
Date of Patent:
Jul. 27, 2021

Filed:

Jan. 22, 2019

Characterizing and simulating library gates to enable identification and elimination of electromigration violations in semiconductor chips

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Leon Sigal, Monsey, NY (US);

David Kadzov, South Burlington, VT (US);

Nagashyamala R. Dhanwada, Tenafly, NJ (US);

James Douglas Warnock, Somers, NY (US);

Assignee:

International Business Machines Corporation, Armonk, NY (US);

Attorneys:

Erik Johnson

Otterstedt, Wallace & Kammer, LLP

Primary Examiner:

Leigh M Garbowski

Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/398 (2020.01); G06F 30/3308 (2020.01); G06F 30/3312 (2020.01); G06F 30/337 (2020.01); G06F 30/36 (2020.01); G06F 119/10 (2020.01); G06F 30/33 (2020.01); G06F 111/20 (2020.01); G06F 119/06 (2020.01); G06F 119/12 (2020.01); G06F 119/02 (2020.01); G06F 119/08 (2020.01); G06F 119/18 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/337 (2020.01); G06F 30/3308 (2020.01); G06F 30/3312 (2020.01); G06F 30/33 (2020.01); G06F 30/36 (2020.01); G06F 2111/20 (2020.01); G06F 2119/02 (2020.01); G06F 2119/06 (2020.01); G06F 2119/08 (2020.01); G06F 2119/10 (2020.01); G06F 2119/12 (2020.01); G06F 2119/18 (2020.01);
Abstract

A method and system for improving the performance of a computer in identifying and mitigating electromigration violations of a semiconductor device. A set of library gates is obtained and parasitic layout extraction is performed for each gate in the set of library gates to generate an extracted netlist. One or more passes of an electromigration analysis of the extracted netlist are performed to characterize each gate over a set of input parameters and to generate a maximum slew rate (MAX_SLEW) table and a maximum capacitance (MAX_CAP) table.

Find Patent Forward Citations

Loading…