The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 20, 2021

Filed:

Feb. 21, 2020
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Katsuhisa Tanaka, Tsukuba, JP;

Shinya Kyogoku, Yokohama, JP;

Ryosuke Iijima, Setagaya, JP;

Shinichi Kimoto, Tsukuba, JP;

Assignee:

KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/04 (2006.01); H01L 29/66 (2006.01); H01L 29/16 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7813 (2013.01); H01L 21/047 (2013.01); H01L 29/1608 (2013.01); H01L 29/66068 (2013.01);
Abstract

A semiconductor device according to an embodiment includes: a SiC layer having a first plane, a second plane, a first trench located on a first plane side, an n-type first SiC region, a p-type second SiC region between the first SiC region and the first plane, an n-type third SiC region between the second SiC region and the first plane, and a p-type fourth SiC region between the first SiC region and the first plane, at least a portion of the fourth SiC region located in the second SiC region, the fourth SiC region having a higher p-type impurity concentration than the second SiC region; a gate electrode in the first trench; a first electrode located on the first plane side; and a second electrode located on a second plane side. A depth of the fourth SiC region increases with distance from the first trench.


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