The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 20, 2021

Filed:

Dec. 03, 2019
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Shanghai, CN;

Inventors:

Zhuofan Chen, Shanghai, CN;

Haiyang Zhang, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/66 (2006.01); H01L 45/00 (2006.01); H01L 27/24 (2006.01); H01L 21/762 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/76224 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823878 (2013.01); H01L 27/2436 (2013.01); H01L 29/0649 (2013.01); H01L 29/42364 (2013.01); H01L 29/66795 (2013.01); H01L 29/7856 (2013.01); H01L 45/124 (2013.01); H01L 45/146 (2013.01); H01L 45/16 (2013.01);
Abstract

The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method may include: providing a semiconductor structure, where the semiconductor structure includes a semiconductor fin and an interlayer dielectric layer covering the semiconductor fin, the interlayer dielectric layer having an opening exposing a part of the semiconductor fin; forming a data storage layer at a bottom portion and a side surface of the opening; and filling a conductive material layer in the opening on the data storage layer. The present disclosure facilitate the manufacturing process of the semiconductor device and improves processing compatibility with the CMOS technology.


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