The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 20, 2021

Filed:

Jul. 03, 2017
Applicants:

National Institute of Advanced Industrial Science and Technology, Tokyo, JP;

Wacom R&d Corporation, Tokyo, JP;

Inventors:

Mitsue Takahashi, Ibaraki, JP;

Shigeki Sakai, Ibaraki, JP;

Masaki Kusuhara, Tokyo, JP;

Masayuki Toda, Tokyo, JP;

Masaru Umeda, Tokyo, JP;

Yoshikazu Sasaki, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/1159 (2017.01); H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 21/311 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 27/11587 (2017.01); H01L 21/033 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1159 (2013.01); H01L 21/0337 (2013.01); H01L 21/31116 (2013.01); H01L 27/11587 (2013.01); H01L 29/40111 (2019.08); H01L 29/4983 (2013.01); H01L 29/516 (2013.01); H01L 29/6653 (2013.01); H01L 29/6684 (2013.01); H01L 29/66553 (2013.01); H01L 29/78391 (2014.09);
Abstract

A semiconductor memory element is provided including a laminated structure, in which a memory member and a conductor are superposed on a semiconductor substrate. The memory member has a bottom surface in contact with the semiconductor substrate, an upper surface in contact with the conductor, and side surfaces, which are in contact with and surrounded by a partition wall; the bottom surface of the memory member has a width of equal to or not more than 100 nm; a shortest distance between the conductor and the semiconductor substrate is twice or more of the width of the bottom surface of the memory member; the side surface of the memory member has a width, which is either the same as the width of the bottom surface and constant at any position above the bottom surface, or the widest at a position other than the bottom surface and above the bottom surface.


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