3d nor memory having vertical gate structures

Abstract

A memory device comprises a plurality of stacks of bit lines alternating with insulating strips over an insulating layer on a substrate, and a plurality of vertical gate structures disposed between the stacks. Vertical channel structures and memory elements are disposed between outside surfaces of the vertical gate structures and sidewalls of insulating strips in the stacks of bit lines. The vertical channel structures provide channels between adjacent bit lines in the stacks. A plurality of word line transistors is disposed over and connected to respective vertical gate structures. A plurality of word lines is disposed over and connected to the word line transistors. The memory device comprises circuitry connected to the bit lines to apply bit line and source line voltages to the bit lines.