logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11069691 B1

PDFFull Text
Date of Patent:
Jul. 20, 2021

Filed:

Mar. 06, 2018

Memory cell array with large gate widths

Applicant:

Globalfoundries U.s. Inc., Santa Clara, CA (US);

Inventor:

Shady Ahmed Abdelwahed Ahmed Elshafie, Dresden, DE;

Assignee:

GLOBALFOUNDRIES U.S. Inc., Santa Clara, CA (US);

Attorneys:

Yee Tze Lim

Hoffman Warnick LLC

Primary Examiner:

Hsin Yi Hsieh

Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 27/02 (2006.01); H01L 29/10 (2006.01); H01L 27/12 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01); H01L 21/84 (2006.01); H01L 21/306 (2006.01); H01L 21/02 (2006.01); H01L 21/3213 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/30604 (2013.01); H01L 21/31111 (2013.01); H01L 21/32133 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 21/845 (2013.01); H01L 23/5283 (2013.01); H01L 27/0207 (2013.01); H01L 27/1203 (2013.01); H01L 27/1211 (2013.01); H01L 29/0847 (2013.01); H01L 29/1033 (2013.01); H01L 29/41783 (2013.01);
Abstract

An integrated circuit is provided with a memory cell array comprising poly lines, semiconductor lines extending in a first direction and transistor devices, wherein gates of the transistor device are formed in portions of the poly lines and channels of the transistor devices are formed in the semiconductor lines and wherein at least one portion of at least one of the poly lines runs across at least one of the semiconductor lines in a second direction inclined to a direction perpendicular to the first direction at an inclination angle of more than, for example, 5° or 10°, as measured from the direction perpendicular to first direction.

Find Patent Forward Citations

Loading…