The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 20, 2021

Filed:

Mar. 27, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Dae-suk Lee, Suwon-si, KR;

Hak-seung Lee, Seoul, KR;

Dong-chan Lim, Hwaseong-si, KR;

Tae-seong Kim, Suwon-si, KR;

Kwang-jin Moon, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 21/768 (2006.01); H01L 23/31 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/76832 (2013.01); H01L 21/76898 (2013.01); H01L 23/3128 (2013.01); H01L 23/5226 (2013.01); H01L 23/53295 (2013.01); H01L 24/08 (2013.01); H01L 24/16 (2013.01); H01L 25/18 (2013.01);
Abstract

Semiconductor chips and methods of manufacturing the same are provided. The semiconductor chip includes a substrate, an interlayer insulation layer including a bottom interlayer insulation layer on an upper surface of the substrate and a top interlayer insulation layer on the bottom interlayer insulation layer, an etch stop layer between the bottom interlayer insulation layer and the top interlayer insulation layer, a landing pad on the interlayer insulation layer, and a through via connected to the landing pad through the substrate, the interlayer insulation layer, and the etch stop layer. The etch stop layer is isolated from direct contact with the landing pad.


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