The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 20, 2021

Filed:

Sep. 20, 2019
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Chiaki Dono, Tokyo, JP;

Chikara Kondo, Tokyo, JP;

Ryo Fujimaki, Tokyo, JP;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/00 (2006.01); G01R 31/3177 (2006.01); G11C 29/12 (2006.01); H01L 25/18 (2006.01); G11C 11/4093 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3177 (2013.01); G11C 11/4093 (2013.01); G11C 29/12 (2013.01); H01L 25/18 (2013.01);
Abstract

Disclosed herein are systems, methods, and devices that enable access to a first interface control circuit via test probes of a second interface. In some embodiments a memory device includes a first interface including first ports that are inaccessible to a test probe. The memory device also includes a first interface control circuit configured to control operation of the first interface. The memory device further includes a second interface including second ports. At least a portion of the second ports include test pads that are accessible to the test probe. In addition, the memory device includes a multiplexer configured to operably couple the first interface and at least a portion of the second interface to the first interface control circuit. The multiplexer is configured to selectively enable test probe access to the first interface control circuit via the test pads.


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