Wide frequency range step size programmability for delay-locked loops using variable bias voltage generation

Abstract

Described is a delay-locked loop which includes a frontend circuit configured to output a control voltage based on an input clock and a feedback clock and a delay line circuit connected to the frontend circuit. The delay line circuit configured to generate a bias voltage based on the control voltage and a step size, where the bias voltage is variable based on the step size, and apply at least one level of delay on the input clock based on the bias voltage to generate an output clock, where the feedback clock being based on the output clock and where the input clock is aligned with the feedback clock by delaying the phase of the output clock until phase lock.