The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 13, 2021

Filed:

Apr. 27, 2020
Applicant:

Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;

Inventors:

Wen Chung Yang, Miaoli County, TW;

Shih Hsi Chen, Hsinchu County, TW;

Wei-Chang Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 27/11521 (2017.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7883 (2013.01); H01L 27/11521 (2013.01); H01L 29/40114 (2019.08); H01L 29/42336 (2013.01); H01L 29/66825 (2013.01);
Abstract

A memory device and a manufacturing method of the memory device are provided. The manufacturing method includes steps below. A plurality of stack structures including a tunneling dielectric layer and a floating gate are formed on a substrate. A liner material layer including a nitride liner layer is formed on the substrate. A top surface of the nitride liner layer is lower than a top surface of the floating gate and is higher than a top surface of the tunneling dielectric layer. An isolation material layer covering the liner material layer is formed on the substrate. The isolation material layer is oxidized, and a portion of the isolation material layer is removed to form an isolation structure. An inter-gate dielectric layer covering the stack structures and the isolation structure is formed on the substrate. A control gate covering the inter-gate dielectric layer is formed on the substrate.


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