The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 13, 2021

Filed:

Oct. 15, 2019
Applicants:

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventor:

Nan Wang, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1037 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 29/6681 (2013.01); H01L 29/785 (2013.01);
Abstract

Disclosed are a semiconductor structure and a method for forming same. A forming method includes: forming a first inside wall in a first groove; etching an initial channel laminated layer and an initial fin after the first inside wall is formed, where the residual initial fin is used as a fin, and the residual initial channel laminated layer located on the fin is used to form a channel laminated layer, the channel laminated layer includes a composite layer and a channel layer located on the composite layer, and the composite layer includes a first inside wall and a sacrificial layer located on a sidewall of the first inside wall; forming a pseudo gate structure across the channel laminated layer after the fin is formed; forming a source-drain doping layer in channel laminated layers on two sides of the pseudo gate structure; and removing the pseudo gate structure and the sacrificial layer after the source-drain doping layer is formed, and forming a metal gate structure at positions of the pseudo gate structure and the sacrificial layer. The first inside wall provides support for the channel layer. Therefore, even though the channel layer is relatively long, the channel layer cannot easily deform or collapse under the gravity effect, thereby optimizing the electrical performance of the semiconductor structure.


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