The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 13, 2021

Filed:

May. 15, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Harry-Hak-Lay Chuang, Hsinchu County, TW;

Wei-Cheng Wu, Hsinchu County, TW;

Ya-Chen Kao, Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11568 (2017.01); H01L 29/66 (2006.01); H01L 27/11573 (2017.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 29/66545 (2013.01); H01L 21/823842 (2013.01); H01L 29/42368 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01);
Abstract

A memory device includes a semiconductor substrate, a select gate stack, a main gate, a charge trapping layer, and a spacer. The a select gate stack is over the semiconductor substrate. The main gate is over the semiconductor substrate. The charge trapping layer has a first portion between the main gate and the semiconductor substrate. The spacer is on a sidewall of the main gate. At least a portion of the main gate is between the spacer and the select gate stack, and a lowermost surface of the spacer is above a lowermost surface of the main gate.


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