The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 13, 2021

Filed:

Dec. 05, 2019
Applicant:

Pep Innovation Pte. Ltd., Singapore, SG;

Inventor:

Jimmy Chew, Singapore, SG;

Assignee:

PEP INNOVATION PTE. LTD., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 21/02 (2006.01); H01L 21/78 (2006.01); H01L 23/528 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/561 (2013.01); H01L 21/0201 (2013.01); H01L 21/568 (2013.01); H01L 21/78 (2013.01); H01L 23/3114 (2013.01); H01L 23/3121 (2013.01); H01L 23/528 (2013.01); H01L 24/94 (2013.01);
Abstract

The embodiments of the present disclosure relate to a packaging method, a panel assembly, a wafer package and a chip package. The semiconductor device packaging method includes: providing at least one wafer including a first surface and a second surface opposite to each other and a side surface connecting the first surface and the second surface, the first surface being an active surface; forming a connection portion on the side surface of the at least one wafer around the wafer, the wafer and the connection portion forming a panel assembly, the connection portion includes a third surface on the same side of the first surface of the wafer and a fourth surface on the same side as the second surface of the wafer, the third surface and the first surface forming a to-be-processed surface of the panel assembly. The packaging method of the embodiments of the present disclosure may improve packaging efficiency and utilization of a wafer.


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