The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 06, 2021

Filed:

Jul. 30, 2019
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventor:

De Kui Qi, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 21/266 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14689 (2013.01); H01L 21/266 (2013.01); H01L 27/14612 (2013.01); H01L 27/14636 (2013.01);
Abstract

A semiconductor structure is provided and includes: a substrate, containing first doping ions and including a photosensitive region and a floating diffusion region; a deeply doped region, in the photosensitive region of the substrate and containing second doping ions; a floating diffusion area, in the floating diffusion region of the substrate and containing third doping ions; a gate structure on the substrate at a junction of the photosensitive region and the floating diffusion region; a sidewall spacer on the photosensitive region of the substrate, and on sidewalls and top of the gate structure in the photosensitive region; a first doped region located in the floating diffusion area and having fourth doping ions; a metal connection layer on the first doped region; an interlayer dielectric layer on the substrate exposed by the gate structure; and a contact plug, in the interlayer dielectric layer and electrically connected to the metal connection layer.


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