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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11056400 B1

PDFFull Text
Date of Patent:
Jul. 06, 2021

Filed:

Oct. 11, 2019

Semiconductor device and method

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chao-Ching Cheng, Hsinchu, TW;

Tzu-Chiang Chen, Hsinchu, TW;

Chen-Feng Hsu, Hsinchu, TW;

Yu-Lin Yang, Baoshan Township, TW;

Tung Ying Lee, Hsinchu, TW;

Chih Chieh Yeh, Taipei, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Attorney:

Slater Matsil, LLP

Primary Examiner:

Fernando L Toledo

Assistant Examiner:

Valerie N Newton

Int. Cl.
CPC ...
H01L 21/82 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 29/775 (2006.01); H01L 29/08 (2006.01); H01L 21/8234 (2006.01); B82Y 10/00 (2011.01);
U.S. Cl.
CPC ...
H01L 21/823807 (2013.01); B82Y 10/00 (2013.01); H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/30604 (2013.01); H01L 21/823412 (2013.01); H01L 21/823814 (2013.01); H01L 27/092 (2013.01); H01L 29/0653 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/42376 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/66772 (2013.01); H01L 29/775 (2013.01); H01L 29/78651 (2013.01); H01L 29/78654 (2013.01); H01L 29/78684 (2013.01); H01L 29/78696 (2013.01); H01L 21/823456 (2013.01);
Abstract

Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.

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