The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 06, 2021

Filed:

Mar. 29, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Cheng-Chien Li, Hsinchu County, TW;

Wei-Shuo Ho, New Taipei, TW;

Huang-Chao Chang, Hsinchu, TW;

Wei-Zhe Jhang, Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 29/6681 (2013.01); H01L 29/66545 (2013.01); H01L 29/7848 (2013.01); H01L 29/7851 (2013.01);
Abstract

A method for forming a FinFET device is described. The method includes the following steps. A substrate is patterned to form fins. Dummy gate stack is formed on the substrate and over the fins, wherein the dummy gate stack may be formed by the following steps: a dummy layer is formed; a first etching step is performed on the dummy layer with a bromine containing etching gas to form a dummy strip; a second etching step is performed on the dummy strip with a chlorine containing etching gas to form the dummy gate stack. The dummy gate stack is replaced with a gate stack.


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