The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 06, 2021
Filed:
Sep. 25, 2019
Kla Corporation, Milpitas, CA (US);
Ardis Liang, Pleasanton, CA (US);
Martin Plihal, Pleasanton, CA (US);
Saravanan Paramasivam, Chennai, IN;
Niveditha Lakshmi Narasimhan, Chennai, IN;
Sandeep Bhagwat, Milpitas, CA (US);
KLA Corporation, Milpitas, CA (US);
Abstract
To evaluate a semiconductor-fabrication process, a semiconductor wafer is obtained that includes die grouped into modulation sets. Each modulation set is fabricated using distinct process parameters. The wafer is optically inspected to identify defects. A nuisance filter is trained to classify the defects as DOI or nuisance defects. Based on results of the training, a first, preliminary process window for the wafer is determined and die structures having DOI are identified in a first group of modulation sets bordering the first process window. The trained nuisance filter is applied to the identified defects to determine a second, revised process window for the wafer. A third, further revised process window for the wafer is determined based on SEM images of specified care areas in one or more modulation sets within the second, revised process window. A report is generated that specifies the third process window.