The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 06, 2021

Filed:

Dec. 30, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Gaspar Mora Porta, Campbell, CA (US);

Michael A Parker, San Jose, CA (US);

Roberto Penaranda Cebrian, Santa Clara, CA (US);

Albert S Cheng, Bellevue, WA (US);

Francesc Guim Bernat, Barcelona, ES;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); G06F 13/366 (2006.01); H04L 12/801 (2013.01); H04L 12/937 (2013.01);
U.S. Cl.
CPC ...
G06F 13/4022 (2013.01); G06F 13/366 (2013.01); H04L 47/10 (2013.01); H04L 49/254 (2013.01);
Abstract

In some embodiments, the invention involves using a weighted arbiter switch to provide fairness in passing input streams through a plurality of input ports to an output port. The weighted arbiter switches may be combined in a hierarchical architecture to enable routing through many levels of switches. Each input port has an associated flow counter to count input stream traffic through the input port. An arbiter switch uses the flow counts and weights from arbiter switches at a lower level in the hierarchy to generate a fairly distributed routing of input streams through the output port. Other embodiments are described and claimed.


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