The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 06, 2021

Filed:

Dec. 05, 2019
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventors:

Wein-Town Sun, Hsinchu County, TW;

Ching-Hsiang Hsu, Hsinchu County, TW;

Assignee:

eMemory Technology Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G06F 12/14 (2006.01); G06F 21/79 (2013.01); G11C 11/16 (2006.01); G11C 13/00 (2006.01); G11C 11/56 (2006.01); G11C 11/4074 (2006.01); G11C 16/12 (2006.01); G11C 16/14 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1408 (2013.01); G06F 12/1425 (2013.01); G06F 21/79 (2013.01); G11C 11/1657 (2013.01); G11C 11/1673 (2013.01); G11C 11/1697 (2013.01); G11C 11/4074 (2013.01); G11C 11/5642 (2013.01); G11C 13/004 (2013.01); G11C 13/0028 (2013.01); G11C 13/0038 (2013.01); G11C 16/12 (2013.01); G11C 16/14 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/34 (2013.01);
Abstract

A storage cell includes a selection circuit, a first memory transistor, and a second memory transistor. The selection circuit is coupled to a source line and a common node. When the selection circuit is turned on, the selection circuit forms an electrical connection between the source line and the common node. The first memory transistor has a first terminal coupled to the common node, a second terminal coupled to a first bit line, and a control terminal coupled to a control line. The second memory transistor has a first terminal coupled to the common node, a second terminal coupled to a second bit line, and a control terminal coupled to the control line. The first memory transistor and the second memory transistor are 2-dimension charge-trapping devices or 3-dimension charge-trapping devices.


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