The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 29, 2021
Filed:
Mar. 07, 2018
Applicant:
X-fab Semiconductor Foundries Ag, Erfurt, DE;
Inventors:
Eng Gek Hee, Sarawak, MY;
Ek Chien Yeo, Sarawak, MY;
Steffen Thiem, Moritzburg, DE;
Choon Swee Tan, Sarawak, MY;
Assignee:
X-FAB SEMICONDUCTOR FOUNDRIES GMBH, Erfurt, DE;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/792 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 29/788 (2006.01); H01L 29/06 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7843 (2013.01); H01L 21/84 (2013.01); H01L 27/1203 (2013.01); H01L 29/0649 (2013.01); H01L 29/66833 (2013.01); H01L 29/788 (2013.01); H01L 29/7849 (2013.01); H01L 29/78654 (2013.01); H01L 29/792 (2013.01);
Abstract
A semiconductor memory device comprising a strained semiconductor layer and a contact etch stop layer, CESL, wherein the strained semiconductor layer and the CESL are both arranged to reduce the probability of an electron tunnelling out of a charge trapping layer of the semiconductor memory device.