Semiconductor power device and manufacturing method thereof

Abstract

A semiconductor power device and a manufacturing method thereof are provided. In the manufacturing method, before the self-aligned silicide process is performed, a gate stacked structure and a spacer are formed on a semiconductor layer having a body region and a source region. The spacer defines a portion of the source region for forming a silicide layer. Subsequently, the self-aligned silicide process is performed with the gate stacked structure and the spacer functioning as a mask to form the silicide layer at the defined portion of the source region. Thereafter, an interconnection structure including an interlayer dielectric layer and a source conductive layer is formed on the semiconductor layer. The source conductive layer is electrically connected to the source region. The silicide layer extends toward the gate stacked structure from a position under the source conductive layer to another position under the interlayer dielectric layer.