The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 29, 2021
Filed:
Nov. 12, 2019
Applicants:
Te-chang Tseng, Hsinchu County, TW;
Riichiro Shirota, Fujisawa, JP;
Inventors:
Riichiro Shirota, Fujisawa, JP;
Yung-Yueh Chiu, New Taipei, TW;
Te-Chang Tseng, Hsinchu County, TW;
Hiroshi Watanabe, Yokohama, JP;
Assignee:
Other;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/16 (2006.01); H01L 29/36 (2006.01); H01L 29/165 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1608 (2013.01); H01L 29/1095 (2013.01); H01L 29/1602 (2013.01); H01L 29/36 (2013.01);
Abstract
A semiconductor device based on SiC-MOSFET realizes high voltage endurance, high current, low breakover voltage, low switching loss and low noise. The SiC-MOSFET is a combination of a Si-MOSFET with high channel mobility and a drift layer formed by SiC with high bulk mobility, so that the first conductive SiC wafer forming the drift layer joins the second conductive Si wafer, excavates out a trench gate in part of the SiC to make the MOSFET, and a second conductive barrier layer is arranged in the Si region adjacent to the SiC.