The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 29, 2021

Filed:

Dec. 13, 2018
Applicant:

Db Hitek Co., Ltd., Seoul, KR;

Inventor:

Chang Eun Lee, Seoul, KR;

Assignee:

DB HITEK CO., LTD., Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1045 (2013.01); H01L 29/0615 (2013.01); H01L 29/0634 (2013.01); H01L 29/0878 (2013.01); H01L 29/1083 (2013.01); H01L 29/1087 (2013.01); H01L 29/6659 (2013.01); H01L 29/66681 (2013.01); H01L 29/66689 (2013.01); H01L 29/7816 (2013.01);
Abstract

A PLDMOS transistor includes a substrate, a P-type drift region disposed on an upper surface of the substrate, a first body region of N-type conductivity, the first body region being disposed on one side of the drift region and having a channel region formed thereon, a drain extension region of P-type conductivity, the drain extension region being disposed on another side of the drift region and being spaced apart from the first body region, a P-type drain region disposed on the drain extension region, a gate structure disposed on the channel region, an N-type buried layer disposed under the drift region and first and second breakdown voltage increasing layers being configured to increase the breakdown voltage by providing reduced surface fields.


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