The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 29, 2021

Filed:

Jan. 03, 2018
Applicant:

Ampere Computing Llc, Santa Clara, CA (US);

Inventors:

Ronen Cohen, Sunnyvale, CA (US);

Alfred Yeung, Fremont, CA (US);

Ojas Dharia, Santa Clara, CA (US);

Assignee:

Ampere Computing LLC, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 23/535 (2006.01); H01L 23/522 (2006.01); H01L 49/02 (2006.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01);
U.S. Cl.
CPC ...
H01L 27/0288 (2013.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01); H01L 23/5223 (2013.01); H01L 23/535 (2013.01); H01L 27/0207 (2013.01); H01L 28/60 (2013.01);
Abstract

A metal-insulator-metal (MIM) capacitor design methodology and system substantially maximizes the benefits of including MIM capacitors in an integrated circuit design while substantially minimizing the negative impacts resulting from increased capacitance. A process analysis is performed on an integrated circuit design to determine a metal layer that is likely to be most adversely affected by the presence of MIM capacitor cells. The MIM capacitor cells are then designed to have specific sizes and orientations based on results of the process analysis, taking the most affected metal layer into consideration. Finally, the MIM capacitor cells are placed at selected locations on the die in an algorithmic fashion in order to satisfy a design target of maximizing coverage area while avoiding interference with signal paths and critical or sensitive components.


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