The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 29, 2021

Filed:

Apr. 23, 2020
Applicant:

Delta Electronics, Inc., Taoyuan, TW;

Inventors:

Hsin-Chang Tsai, Taoyuan, TW;

Chia-Yen Lee, Taoyuan, TW;

Peng-Hsin Lee, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/433 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/4334 (2013.01); H01L 23/3107 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/73267 (2013.01); H01L 2924/0002 (2013.01); H01L 2924/15153 (2013.01);
Abstract

A packaging device including a first semiconductor device, a thermal dissipating component, an encapsulation layer, a via, and a pad. The first semiconductor device includes a substrate, an active region, and an electrode. The active region is disposed between the substrate and the electrode. The substrate has a first surface opposite to the active region, and the electrode has a second surface opposite to the active region. The thermal dissipating component is disposed on the first surface of the substrate. The encapsulation layer encloses the second surface of the electrode and a part of the thermal dissipating component, such that another part of the thermal dissipating component is exposed by the encapsulation layer. The pad is disposed on the encapsulation layer. The via is disposed in the encapsulation layer and connects the pad to the electrode.


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