The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 29, 2021

Filed:

Sep. 18, 2019
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Keita Tsuchiya, Tokyo, JP;

Shuuichi Kariyazaki, Tokyo, JP;

Takashi Kikuchi, Tokyo, JP;

Michiaki Sugiyama, Tokyo, JP;

Yusuke Tanuma, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/36 (2006.01); H01L 23/40 (2006.01); H01L 23/538 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
H01L 23/36 (2013.01); H01L 23/40 (2013.01); H01L 23/5389 (2013.01); H01L 25/18 (2013.01);
Abstract

The semiconductor device includes a wiring substrate, a first and second semiconductor chips, and the heat sink. The wiring substrate has a first surface. The first and second semiconductor chips are disposed on the first surface. The heat sink is disposed on the first surface so as to cover the first semiconductor chip. The heat sink has a second surface and the third surface opposite the first surface. The second surface faces the first surface. The heat sink has a first cut-out portion. The first cut-out portion is formed at a position overlapping with the second semiconductor chip in plan view, and penetrates the heat sink in a direction from the third surface toward the second surface. The second surface is joined to at least four corners of the first surface.


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