The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 29, 2021

Filed:

Feb. 13, 2020
Applicant:

Panjit International Inc., Kaohsiung, TW;

Inventor:

Chung-Hsiung Ho, Kaohsiung, TW;

Assignee:

PANJIT INTERNATIONAL INC., Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 23/13 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/14 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3114 (2013.01); H01L 21/4857 (2013.01); H01L 23/13 (2013.01); H01L 23/142 (2013.01); H01L 23/3121 (2013.01); H01L 23/49811 (2013.01); H01L 23/49822 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01);
Abstract

A chip-scale package device includes a substrate unit, a chip unit, and an electrical insulator. The substrate unit has opposite first and second surfaces, and a receiving space defined by a space-defining surface. The chip unit is disposed in the receiving space, and includes a chip and first and second electrodes disposed oppositely on the chip. The electric insulator fills the receiving space to cover the space-defining surface and the chip unit and to expose the first electrode. The first and second surfaces and the space-defining surface are electrically connected to one another, and the second electrode is electrically connected to the space-defining surface.


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