Three-dimensional memory device with depletion region position control and method of erasing same using gate induced leakage

Abstract

Gate-induced leakage current that is independent of a location of a physical p-n junction between a semiconductor channel and a source/drain region can be provided within a NAND string of a three-dimensional memory device by employing at least one leakage current control circuit that is activated during an erase operation. During the erase operation, an accumulation region and an inversion region can be formed between a vertically-neighboring pair of electrically conductive layers with a depletion region therebetween. The depletion region can generate and inject majority charge carriers into the semiconductor channel during the erase operation. The depletion region can be formed in the source region or in the drain region and may not overlap with a physical p-n junction. Thus, the charge injection location can be independent of the location of the physical p-n junction.