Memory cell arrangement and methods thereof

Abstract

A memory cell arrangement is provided that may include: a control circuit configured to supply a precondition signal and one of at least two write signals to a memory cell of the memory cell arrangement, the memory cell including a field-effect transistor structure and a remanent-polarizable layer, wherein the precondition signal is configured to bring the memory cell from an actual condition into a predefined condition, wherein the predefined condition is associated with a predefined threshold voltage of the field-effect transistor structure of the memory cell, and wherein the at least two write signals are configured to write the memory cell selectively into a first memory state or into a second memory state.