The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 29, 2021
Filed:
Jul. 26, 2019
Applicant:
Cadence Design Systems, Inc., San Jose, CA (US);
Inventors:
Elias Lee Fallon, Allison Park, PA (US);
Wangyang Zhang, Allison Park, PA (US);
Sheng Qian, Sunnyvale, CA (US);
Assignee:
Cadence Design Systems, Inc., San Jose, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/398 (2020.01); G06N 20/00 (2019.01); G06F 30/20 (2020.01); G06F 30/27 (2020.01); G06F 30/373 (2020.01); G06F 30/337 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06N 20/00 (2019.01); G06F 30/20 (2020.01); G06F 30/27 (2020.01); G06F 30/337 (2020.01); G06F 30/373 (2020.01);
Abstract
The present disclosure relates to a computer-implemented method for electronic circuit design. Embodiments may include receiving, using at least one processor, data corresponding to an electronic design schematic. Embodiments may further include analyzing the data to learn one or more device size parameters, a range of parameters, or a matching relationship of parameters based upon, at least in part, the electronic design schematic or the electronic design layout, wherein analyzing occurs without user action.