Determining an inactive memory bank during an idle memory cycle to prevent error cache overflow

Abstract

A method of writing data into a memory device comprising utilizing a pipeline to process write operations of a first plurality of data words addressed to a plurality of memory banks, wherein each of the plurality of memory banks is associated with a counter. The method also comprises writing a second plurality of data words and associated memory addresses into an error buffer, wherein the error buffer is associated with the plurality of memory banks and wherein further each data word of the second plurality of data words is either awaiting write verification associated with a bank from the plurality of memory banks or is to be re-written into a bank from the plurality of memory banks. Further, the method comprises maintaining a count in each of the plurality of counters for a respective number of entries in the error buffer corresponding to a respective memory bank.