The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 22, 2021

Filed:

Oct. 18, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chao-Ching Cheng, Hsinchu, TW;

Yu-Lin Yang, Baoshan Township, TW;

Wei-Sheng Yun, Taipei, TW;

Chen-Feng Hsu, Hsinchu, TW;

Tzu-Chiang Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 29/04 (2006.01); H01L 29/775 (2006.01); H01L 29/08 (2006.01); B82Y 10/00 (2011.01);
U.S. Cl.
CPC ...
H01L 29/66553 (2013.01); B82Y 10/00 (2013.01); H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/30608 (2013.01); H01L 29/045 (2013.01); H01L 29/0649 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/42376 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/66772 (2013.01); H01L 29/775 (2013.01); H01L 29/78618 (2013.01); H01L 29/78651 (2013.01); H01L 29/78654 (2013.01); H01L 29/78684 (2013.01); H01L 29/78696 (2013.01); H01L 2029/42388 (2013.01);
Abstract

A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.


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