The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 22, 2021

Filed:

Jul. 30, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chia-Wen Chang, Taipei, TW;

Hong-Nien Lin, Hsinchu, TW;

Chien-Hsing Lee, Hsinchu, TW;

Chih-Sheng Chang, Hsinchu, TW;

Ling-Yen Yeh, Hsinchu, TW;

Wilman Tsai, Saratoga, CA (US);

Yee-Chia Yeo, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 27/06 (2006.01); H01L 27/1159 (2017.01); H01L 29/417 (2006.01); H01L 27/088 (2006.01); H01L 21/28 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0629 (2013.01); H01L 21/82345 (2013.01); H01L 21/823431 (2013.01); H01L 21/823456 (2013.01); H01L 27/0886 (2013.01); H01L 27/1159 (2013.01); H01L 28/40 (2013.01); H01L 29/40111 (2019.08); H01L 29/41791 (2013.01); H01L 29/42376 (2013.01); H01L 29/4958 (2013.01); H01L 29/4966 (2013.01); H01L 29/4975 (2013.01); H01L 29/516 (2013.01); H01L 29/517 (2013.01); H01L 29/6684 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01); H01L 29/78391 (2014.09); H01L 29/66545 (2013.01);
Abstract

A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.


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