The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 22, 2021

Filed:

Jan. 14, 2020
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Wei-Chen Wang, Taipei, TW;

Ping-Hsien Lin, Taipei, TW;

Tse-Yuan Wang, Kinmen County, TW;

Yuan-Hao Chang, Taipei, TW;

Tei-Wei Kuo, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 16/901 (2019.01); G06F 12/10 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0616 (2013.01); G06F 3/064 (2013.01); G06F 3/0679 (2013.01); G06F 12/10 (2013.01); G06F 16/9024 (2019.01); G06F 2212/1036 (2013.01);
Abstract

A memory management method includes: performing a bloom filtering operation on a plurality of logic block addresses to determine a read and written frequency of each of the logic block addresses; setting a first program/erase (P/E) cycle threshold and a second P/E cycle threshold value, wherein the first P/E cycle threshold value is smaller than the second P/E cycle threshold value; dividing each of physical memory blocks into a first type memory block, a second type memory block or a third type memory block according to the first P/E cycle threshold value and the second P/E cycle threshold value; and, allocating each of the logic block addresses to the first type memory block, the second type memory block or the third type memory block according to the read and written frequency of corresponding logic block addresses.


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