The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2021

Filed:

May. 08, 2019
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Ingo Muri, Villach, AT;

Johannes Konrad Baumgartl, Riegersdorf, AT;

Oliver Hellmund, Neubiberg, DE;

Jacob Tillmann Ludwig, Villach, AT;

Iris Moder, Villach, AT;

Thomas Christian Neidhart, Klagenfurt, AT;

Gerhard Schmidt, Wernberg-Wudmath, AT;

Hans-Joachim Schulze, Taufkirchen, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/36 (2006.01); H01L 21/223 (2006.01); H01L 21/02 (2006.01); H01L 21/225 (2006.01); H01L 29/167 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 29/36 (2013.01); H01L 21/02236 (2013.01); H01L 21/02381 (2013.01); H01L 21/2236 (2013.01); H01L 21/2253 (2013.01); H01L 21/26513 (2013.01); H01L 29/167 (2013.01);
Abstract

A method of manufacturing a semiconductor device includes providing a semiconductor substrate having opposing first and second main surfaces and first and second dopants. A covalent atomic radius of a material of the substrate is i) larger than a covalent atomic radius of the first dopant and smaller than that of the second dopant, or ii) smaller than the covalent atomic radius of the first dopant and larger than that of the second dopant. A vertical extension of the first dopant into the substrate from the first main surface ends at a bottom of a substrate portion at a first vertical distance to the first main surface. The method further includes forming a semiconductor layer on the first main surface, forming semiconductor device elements in the semiconductor layer, and reducing a thickness of the substrate by removing material from the second main surface at least up to the substrate portion.


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