The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2021

Filed:

Jul. 25, 2019
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Chen Wu, Leuven, BE;

Peter Rabkin, Cupertino, CA (US);

Yangyin Chen, Leuven, BE;

Masaaki Higashitani, Cupertino, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01); H01L 25/065 (2006.01); H01L 25/18 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/7682 (2013.01); H01L 21/76837 (2013.01); H01L 21/76852 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 24/08 (2013.01); H01L 24/16 (2013.01); H01L 24/80 (2013.01); H01L 24/81 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/81815 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06544 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01);
Abstract

A bonded assembly includes a first semiconductor die including a first substrate, first semiconductor devices located on the first substrate, first dielectric material layers located on the first semiconductor devices and embedding first metal interconnect structures, and first through-substrate via structures extending through the first substrate and contacting a respective first metal interconnect structure. Each of the first through-substrate via structures laterally surrounds a respective core cavity that contains a void or a dielectric fill material portion. The bonded assembly includes a second semiconductor die attached to the first semiconductor die, and including a second substrate, second semiconductor devices located on the second substrate, second dielectric material layers located on the second semiconductor devices and embedding second metal interconnect structures, and bonding pad structures electrically connected to a respective one of the second metal interconnect structures and bonded to a respective first through-substrate via structure.


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