The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2021

Filed:

Dec. 30, 2016
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventor:

Darrell Truhitte, Phoenix, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/00 (2006.01); H01L 21/78 (2006.01); H01L 23/544 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 24/96 (2013.01); H01L 21/31138 (2013.01); H01L 21/4821 (2013.01); H01L 21/4853 (2013.01); H01L 21/56 (2013.01); H01L 21/78 (2013.01); H01L 23/544 (2013.01); H01L 21/4828 (2013.01); H01L 21/561 (2013.01); H01L 2223/54453 (2013.01);
Abstract

A method of forming a plurality of semiconductor packages includes providing an array of unsingulated semiconductor packages that are at least partially encapsulated in an encapsulant. The array of unsingulated semiconductor packages may be coupled with a lead frame or a substrate. A first plurality of singulation lines are simultaneously etched in the encapsulant through slits in an etch mask using a plasma etching process and a fixture coupled with the array. A second plurality of parallel singulation lines may also be etched. The first and second pluralities of singulation lines may include substantially straight or arcuate lines. The second plurality of parallel singulation lines may be substantially perpendicular to the first plurality of parallel singulation lines and be formed using the plasma etching process, the fixture, and an etch mask. The formation of singulation lines in the array singulates the array into a plurality of singulated semiconductor packages.


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