The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2021

Filed:

May. 08, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Yann Mignot, Slingerlands, NY (US);

Muthumanickam Sankarapandian, Niskayuna, NY (US);

Yongan Xu, Niskayuna, NY (US);

Joe Lee, Albany, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 21/311 (2006.01); H01L 21/321 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76877 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/3212 (2013.01); H01L 21/7684 (2013.01); H01L 21/76816 (2013.01); H01L 23/5226 (2013.01);
Abstract

A method is presented for forming interlayer connections in a semiconductor device. The method includes patterning an etch stack to provide for a plurality of interlayer connections, etching guide layers following the etch stack to a first capping layer to form a plurality of guide openings, concurrently exposing a first plurality of conductive lines and a second plurality of conductive lines to form a plurality of interlayer connection openings by etching through the plurality of guide openings to remove the first capping layer, an interlayer dielectric, and a second capping layer, and depositing a metal fill in the plurality of interlayer connection openings to form the plurality of interlayer connections.


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