The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 15, 2021
Filed:
Dec. 14, 2018
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 19/00 (2006.01); G11C 7/00 (2006.01); G11C 7/06 (2006.01); H03K 3/037 (2006.01); G11C 7/10 (2006.01); H04L 7/00 (2006.01); G11C 11/16 (2006.01); H04B 1/16 (2006.01); G11C 7/08 (2006.01);
U.S. Cl.
CPC ...
G11C 7/065 (2013.01); G11C 7/062 (2013.01); G11C 7/08 (2013.01); G11C 7/106 (2013.01); G11C 7/1087 (2013.01); G11C 11/165 (2013.01); H03K 3/037 (2013.01); H04B 1/16 (2013.01); H04L 7/0037 (2013.01);
Abstract
Described is an apparatus to widen or improve a common mode range of a strong arm latch (SAL). In some embodiments, the SAL comprises a master-slave architecture with a common latch. The apparatus includes: a sampler to sample an input with a first clock, and to provide a sampled output on a node. The SAL is to receive the sampled output on the node, and to sample the sampled output according to a second clock. The apparatus comprises a digital-to-analog converter (DAC) coupled to the node, wherein the DAC is to adjust a common mode of the sampled output according to a digital control to the DAC.