The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2021

Filed:

Dec. 15, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Zhenyu Zhu, Folsom, CA (US);

Chai Huat Gan, Bukit Mertajam, MY;

Mikal Hunsaker, El Dorado Hills, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 13/42 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0632 (2013.01); G06F 3/061 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G06F 13/1694 (2013.01); G06F 13/4282 (2013.01); G06F 2212/7206 (2013.01); G06F 2213/0002 (2013.01); G06F 2213/0024 (2013.01);
Abstract

A first signal may be received from a memory device at a first interconnect terminal of a number of interconnect terminals via a serial communication interface that indicates the memory device includes a NAND type memory device. Whether a second signal that indicates the NAND type memory device is initialized has been received from the memory device at a second interconnect terminal of the number of interconnect terminals may be determined. An operation associated with the NAND type memory device may be performed at the second interconnect terminal and a third interconnect terminal in response to determining the second signal has been received from the memory device indicating the NAND type memory device is initialized.


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