The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 2021

Filed:

Nov. 01, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kaushik Dasgupta, Hillsboro, OR (US);

Chuanzhao Yu, Phoenix, AZ (US);

Chintan Thakkar, Portland, OR (US);

Saeid Daneshgar, Portland, OR (US);

Hyun Yoon, Gilbert, AZ (US);

Xi Li, Chandler, AZ (US);

Anandaroop Chakrabarti, Hillsboro, OR (US);

Stefan Shopov, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01F 27/29 (2006.01); H03F 3/60 (2006.01); H01F 17/00 (2006.01); H03F 3/45 (2006.01); H03H 7/42 (2006.01);
U.S. Cl.
CPC ...
H03F 3/604 (2013.01); H01F 17/0013 (2013.01); H01F 27/29 (2013.01); H03F 3/45179 (2013.01); H03H 7/42 (2013.01); H03F 2200/451 (2013.01); H03F 2203/45228 (2013.01); H03F 2203/45731 (2013.01);
Abstract

An on-chip transformer circuit is disclosed. The on-chip transformer circuit comprises a primary winding circuit comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon in a first dielectric layer of a substrate; and a secondary winding circuit comprising at least one turn of a secondary conductive winding arranged as a second N-sided polygon in a second, different, dielectric layer of the substrate. In some embodiments, the primary winding circuit and the secondary winding circuit are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding, wherein the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding.


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