The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 2021

Filed:

Jun. 24, 2019
Applicant:

Sumitomo Electric Device Innovations, Inc., Kanagawa, JP;

Inventor:

Fumio Yamada, Yokohama, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/32 (2013.01); H01L 24/08 (2013.01); H01L 24/28 (2013.01); H01L 2224/26 (2013.01); H01L 2224/32059 (2013.01); H01L 2924/014 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/38 (2013.01);
Abstract

A semiconductor device including a mounting substrate, a semiconductor chip, a rear-surface metal layer, an AuSn solder layer, and a solder blocking metal layer, is disclosed. The semiconductor chip is mounted on the mounting substrate, and includes front and rear surfaces, and a heat generating element. The rear-surface metal layer includes gold (Au). The AuSn solder layer is located between the mounting substrate and the rear surface to fix the semiconductor chip to the mounting substrate. The solder blocking metal layer is located between the rear surface and the mounting substrate, and in a non-heating region excluding a heating region in which the heat generating element is formed. The solder blocking metal layer includes at least one of NiCr, Ni and Ti and extends to an edge of the semiconductor chip. A void is provided between the solder blocking metal layer and the AuSn solder layer.


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