The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 2021

Filed:

Mar. 28, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Xiaoyu Ruan, Folsom, CA (US);

William A. Stevens, Jr., Folsom, CA (US);

David Novick, Beaverton, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/73 (2013.01); G06F 21/64 (2013.01); G06F 21/57 (2013.01); G06F 8/654 (2018.01); G06F 9/44 (2018.01); G06F 8/60 (2018.01);
U.S. Cl.
CPC ...
G06F 21/572 (2013.01); G06F 8/654 (2018.02); G06F 21/575 (2013.01); G06F 21/64 (2013.01); G06F 21/73 (2013.01);
Abstract

Embodiments described herein enable independently recoverable security for processor and peripheral communication, enabling a processor without native non-volatile memory to generate and recover credentials in response to a firmware update. The processor and peripheral can each have credentials burned into secure fuses. The processor can derive a shared secret from the secure fuses using security attributes that are based on the security version number of firmware within the processor and the peripherals to which the processor is to security communicate. The processor and peripherals can generate ephemeral session keys from the shared secret and nonces. The ephemeral session keys can be used to secure communications between the processor and the peripherals.


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