The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 2021

Filed:

Oct. 11, 2018
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Paul Stonelake, San Jose, CA (US);

Bryan T. Silbermann, San Mateo, CA (US);

Frank F Ross, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G11C 11/406 (2006.01); G06F 12/1009 (2016.01); G06F 13/42 (2006.01); G06F 12/02 (2006.01); G06F 13/20 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1689 (2013.01); G06F 12/1009 (2013.01); G06F 13/1673 (2013.01); G06F 13/4243 (2013.01); G11C 11/40607 (2013.01); G11C 11/40611 (2013.01);
Abstract

A computing system having memory components, including first memory and second memory, wherein the first memory is available to a host system for read and write access over a memory bus during one or more of a first plurality of windows. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, from a driver of the host system, a request regarding a page of data stored in the second memory; responsive to the request, transfer the page from the second memory to a buffer; and write the page from the buffer to the first memory, wherein the page is written to the first memory during at least one of a second plurality of windows corresponding to a refresh timing for the memory bus, and the refresh timing is controlled at the host system.


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