Multi-threaded architecture for memory controller data paths

Abstract

A memory controller includes a large combinational cloud to serve multi-core-to-multi-bank memory accesses which causes congestion and routing delays at physical design level especially in lower technology nodes thus limiting the frequency of operation. Present invention proposes an architecture to process sequences of access requests from multiple processing cores using alternating processing to generate sequences of granted access requests to one or more memory banks. For each processing core, first and second buffers store access requests. When an access request from one buffer is granted, that buffer is configured to receive a new access request and processing is performed to determine whether to grant an access request stored in the other buffer. The invention can maintain optimal bandwidth while providing desired sequences of the granted access requests and solving physical congestion issues.