Zero static high-speed, low power level shifter

Abstract

Described is a high speed, low power level shifter circuit which includes a level shifter coupled to a sensing circuit. The level shifter includes a pair of source transistors, a pair of input transistors, and a pair of switching circuits connected between the source transistors and the input transistors. The sensing circuit turns off a switching circuit on an active side of the level shifter based on detecting that an output voltage of the level shifter has completed a voltage level transition from a first logic level voltage to a second logic level voltage. An open circuit is established on the active side and turns off the pair of source transistors. The other switching circuit is turned on. Static current flow on the active side of the level shifter is stopped and the output voltage is latched to a voltage representative of the second logic level voltage.