The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 2021

Filed:

May. 21, 2020
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Zhixin Cui, Nagoya, JP;

Masatoshi Nishikawa, Nagoya, JP;

Yanli Zhang, San Jose, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11524 (2017.01); H01L 27/1157 (2017.01); H01L 27/11582 (2017.01); H01L 27/11556 (2017.01); H01L 27/11565 (2017.01); H01L 27/11529 (2017.01); H01L 27/11575 (2017.01); H01L 27/11578 (2017.01); H01L 21/28 (2006.01); H01L 27/11519 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11524 (2013.01); H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11529 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11575 (2013.01); H01L 27/11578 (2013.01); H01L 27/11582 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08);
Abstract

A three-dimensional memory device includes alternating stacks of electrically conductive strips and spacer strips located over a substrate and laterally spaced apart among one another by memory stack assemblies. The spacer strips may include air gap strips or insulating strips. Each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion regions. Each of the lateral protrusion regions comprises a respective curved charge storage element. The charge storage elements may be discrete elements located within a respective lateral protrusion region, or may be a portion of a charge storage material layer that extends vertically over multiple electrically conductive strips. Each of the memory stack assemblies may include two rows of vertical semiconductor channels that laterally overlie a respective vertical stack of charge storage elements.


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